In plasma etching, a known problem resulting from electric charge buildup is the development of pockets on a dielectric interface which functions as an etch barrier. This “notching phenomenon” limits the aspect ratios of trenches such as those needed for micromechanical structures, because the overetching times allowed without the development of “notches” or “pockets” become progressively shorter as the aspect ratio (ratio of depth to width) increases. Therefore, for a process that is reliable in production, values of approx. 5:1 to 10:1 are currently thought to be the aspect ratio limit, depending on the geometry of the structure, so that yaw rate sensors, for example, are implemented not by using optimum layer thicknesses of more than 20 μm but instead with epipolysilicon layers approx. 10 μm to 15 μm thick, thus severely restricting the design and performance of these components.
FIG. 1 illustrates the cause of the occurrence of pockets. Electrons strike the surface that is to be etched, i.e., etching layer 61 of a substrate 19 essentially in an undirected manner and are absorbed by the side walls of the etched structures, in particular in the upper portions of trenches having a high aspect ratio. Positively charged ions, however, strike surface 61 almost perpendicularly and in a directed manner, so that a high percentage of ions reaches the bottom of the trench. This directed ion incidence is ultimately the cause of the desired etching anisotropy; however, vertical walls cannot be etched. As long as the etching base is still made of silicon, for example, this does not have any serious consequences. Electrons absorbed by the upper portion of the side wall simply migrate downward in the conductive silicon to the etching base, where they neutralize the positively charged incident ions. However, as soon as a dielectric interface 60, which acts an etch barrier, is reached, this equalizing current is no longer able to reach the ions trapped at dielectric interface 60, resulting in strong fields between the etching base and the side walls of the structure. To an increasing extent, these fields deflect the following ions into the silicon-dielectric transitional area, which is then the driving factor in the development of pockets.
To overcome this problem, it was already proposed in German Published Patent Application No. 199 57 169 that the substrate be given an opportunity to discharge during the pulse pauses by pulsing the substrate bias voltage, i.e., the high- or low-frequency substrate electrode power supplied to the substrate electrode.
Due to the pulsation of the power, i.e., voltage, applied to the substrate electrode, an intermittent ionic current is achieved and the development of harmful charges and resulting electric fields is counteracted by discharge processes in the current pauses. Pocket suppression essentially becomes more effective, the longer the pulse pauses (=discharge times) and at the same time the shorter the pulse periods (=buildup of charges), although this drives up the pulse peak power required during the pulse pauses for the continued progress of anisotropic etching. This approach of supplying the ion acceleration voltage required for anisotropic etching to the substrate electrode in shorter and shorter pulses, which are of a higher voltage accordingly, also results in a loss of process stability, i.e., the occurrence of roughness in the etching base, even including “grass formation” on the etching base. This can be counteracted in part by adjusting the voltage-current ratio for the power supplied to the substrate electrode in favor of a higher voltage and lower current, as is possible in low-frequency biasing at frequencies of 100 kHz to 450 kHz, for example. This procedure in particular enlarges the allowed process window in the direction of a lower pulse-period ratio before roughness begins to occur in the etching base. Unfortunately, this approach has some disadvantages: the plasma impedance is very high; high quality is required of the matching network (matchbox) to accomplish the necessary voltage transformation; the matching itself is unstable and depends to a great extent on the plasma characteristics, and the ion energy spectrum thus generated is broad in relation to the substrate electrode, which makes profile control of anisotropically etched structures difficult.
In summary, the disadvantages listed above are kept within limits and/or partially overcome by low-frequency pulsing of a high-frequency modulated high-frequency power, e.g., 13.56 MHz according to German Published Patent Application No. 199 57 169, and the associated emulation of a low-frequency bias voltage of 100 kHz to 450 kHz, for example, but suppression of pocket formation at a dielectric etch barrier at high aspect ratios of more than 10:1 is still limited.